The present invention relates to a field emission element for use in a field emission display (FED) and method for manufacturing the same.
Conventional field emission elements and a method for manufacturing same as disclosed in Japanese patent No. 2636630 will now be illustrated with reference to FIGS. 3A to 4E.
FIGS. 3A and 3B present a top view of field emission elements and an expanded cross-sectional view of a portion X in FIG. 3A, respectively.
Referring to FIG. 3B, a field emission element includes a glass substrate 10, on which a cathode conductor 11, an insulating layer 12 and a gate 13 are disposed. Provided in the insulating layer 12 and the gate 13 is a gate hole 131, in which a conical emitter 14 is formed on the cathode conductor 11 exposed in the bottom portion of the gate hole 131. Additionally, a resistance layer may be disposed between the emitter 14 and the cathode conductor 11.
The gate 13 is made of a metal such as molybdenum (Mo) and niobium (merely abbreviated as Nb), whereas the emitter 14 is made of a metal such as Mo.
The method for manufacturing the field emission element of FIGS. 3A and 3B will now be described with reference to FIGS. 4A to 4E.
The cathode conductor 11, the insulating layer 12 and the gate 13 are laminated on the glass substrate 10 as shown in FIG. 4A. A photo-resist layer (not shown) is deposited on the gate 13 and are patterned, and then the gate 13 and the insulating layer 12 are etched, to thereby provide gate holes 131, as shown in FIG. 4B. Thereafter, a peeling layer 15 of nickel (Ni) or aluminum (Al) is formed on the surface of the gate 13 by an oblique vapor deposition as shown in FIG. 4C, by which neither Ni nor Al is deposited on the bottom portion of the gate hole 131. Then, the emitter 14 is formed by depositing a material for the emitter 14, i.e., Mo, on the surface of the peeling layer 15 and also toward the gate hole 131 at a right angle with respect to the glass substrate 10 as shown in FIG. 4D. Through such vertical vapor deposition, a Mo layer 16 is formed on the peeling layer 15 and the conical emitter 14 is formed within the gate hole 131. The formation of the conical emitter 14, which conically fills the gate hole 131, is a result of a gradual decrease of hole diameter during the growth of the Mo layer 16 above the gate hole 131. Thereafter, the peeling layer 15 and the Mo layer 16 are removed to complete formation of the field emission element as shown in FIG. 4E.
In a field emission display, by applying a voltage equal to or less than an anode voltage to the gate 13, emission of the electrons from the emitter 14 can be controlled. Therefore, the voltage applied to the gate 13 must be reduced in order to reduce the level of the driving voltage of the field emission display. To accomplish this, the distance d1 (shown in FIG. 3B) between the gate 13 and the tip of the emitter 14 needs to be small, which can be achieved by reducing the diameter of the gate hole 131. The diameter of the gate hole 131 is determined when the gate hole 131 is formed by an etching process shown in FIG. 4B.
In the process shown in FIG. 4B, a photomask aligner, an electron beam exposure apparatus or an ion beam exposure apparatus can be used to form the gate hole 131. The photomask aligner can be advantageous in reducing time in a patterning process by patterning a large area, e.g., 50 mmxc3x9750 mm, at a time, but this device is less suitable in forming a gate hole having a diameter equal to or less than 1 xcexcm. On the other hand, the electron beam exposure apparatus and the ion beam exposure apparatus are more suitable in forming gate holes having a diameter less than 1 xcexcm, but offer a limited patterning area, e.g., 1 mmxc3x971 mm, at a time, thereby requiring greater processing time.
The correlation between the diameter d2 of the gate hole 131 and the height h1 of the corresponding emitter 14 will now be illustrated. When the diameter d2 of the gate hole 131 is reduced, the height h1 of the emitter 14 is also reduced. As evident from the process shown in FIG. 4D, the emitter 14 grows until the gate hole 13 is clogged or covered, and such growth depends on the diameter d2 of the gate hole 131. Additionally, the aspect ratio (the ratio of the height h1 to the diameter of the bottom of the emitter 14) depends on selection of the material of the emitter 14 and conditions for forming the layer. Consequently, a smaller diameter d2 of the gate hole 131 with other conditions fixed, yields a smaller height of the emitter 14.
With reference to FIG. 3B, if the diameter d2 of the gate hole 131 is reduced, while holding the height h2 of the insulating layer 12 fixed, the height h1 of the emitter 14 is also reduced. Consequently, the tip of the emitter 14 is displaced farther from the gate 13, lengthening the distance d1 between the gate 13 and the emitter 14. Therefore, in order to reduce the level of voltage applied to the gate 13, the tip of the emitter 14 needs to be closer to the gate 13 by reducing the height h2, i.e., thickness, of the insulating layer 12, while reducing the diameter d2 of the gate hole 131.
In such a case, when the insulating layer 12 becomes thinner, electrostatic capacity of a capacitor formed by the cathode conductor 11 and the gate 13 becomes greater and reactive power also becomes greater. To reduce the reactive power, an insulation material of smaller dielectric constant can be chosen for the insulating layer 12, but the smaller dielectric constant in general induces low breakdown voltage.
Referring to FIG. 5, there are plotted dielectric constants and the breakdown voltages of silicon based insulating materials formed into layers by the CVD process. In general, an insulating material of a lower dielectric constant has a lower breakdown voltage than that of a higher dielectric constant as shown in FIG. 5. Therefore, the reactive power may be reduced by employing the insulating layer 12 made of insulating material with a lower dielectric constant, however, it suffers from a reduction in the breakdown voltage.
It is, therefore, an object of the present invention to provide a field emission element having a structure which is capable of lowering a driving voltage by reducing a diameter of a gate hole, reducing a reactive power between a gate and a cathode conductor and raising breakdown voltage, and a method for manufacturing such a field emission element, which is capable of providing the gate hole with a diameter equal to or less than 1 xcexcm through the use of a photomask aligner.
In accordance with one aspect of the present invention, there is provided a field emission element, including: a substrate made of an insulating material; a cathode conductor disposed on the substrate; an insulating layer structure disposed on the cathode conductor wherein the insulating layer structure includes a first insulating layer formed on the cathode conductor and a second insulating layer formed on the first insulating layer; a gate disposed on the second insulating layer; a gate hole provided through the gate and the insulating layer structure to expose a portion of the cathode conductor therethrough; and an emitter of a conical shape formed on the exposed portion of the cathode conductor in the gate hole, wherein the first insulating layer is covered by the second insulating layer at a side surface of the gate hole and a dielectric constant of the first insulating layer is different from that of the second insulating layer.
In accordance with another aspect of the invention, there is provided a field emission display, including: a field emission element, having: a substrate made of an insulating material; a cathode conductor disposed on the substrate; an insulating layer structure disposed on the cathode conductor wherein the insulating layer structure includes a first insulating layer formed on the cathode conductor and a second insulating layer formed on the first insulating layer; a gate disposed on the second insulating layer; a gate hole provided through the gate and the insulating layer structure to expose a portion of the cathode conductor therethrough; and an emitter of a conical shape formed on the exposed portion of the cathode conductor in the gate hole, wherein the first insulating layer is covered by the second insulating layer at a side surface of the gate hole and a dielectric constant of the first insulating layer is different from that of the second insulating layer.
In accordance with still another aspect of the invention, there is provided a method for manufacturing a field emission element, including the steps of: forming a cathode conductor on a substrate made of an insulating material; forming a first insulation layer on the cathode conductor; providing a gate hole in the first insulating layer, the cathode conductor being exposed through the gate hole; forming a second insulating layer on the first insulating layer, the cathode conductor exposed in a bottom portion of the gate hole and a side surface of the gate hole; forming a gate on the second insulating layer outside the gate hole; forming a peeling layer on the gate; removing the second insulating layer on the cathode conductor exposed in the bottom portion of the opening; forming a conical emitter by depositing a material for the emitter on the peeling layer and on the cathode conductor in the gate hole; and removing the peeling layer, wherein a dielectric constant of the second insulating layer is different from that of the first insulating layer.